I. Field of the Disclosure
The technology of the disclosure relates to controlling the configuration of a power supply providing power for a digital circuit, such as a central processing unit (CPU) as an example.
II. Background
A circuit may demand a dynamically varying amount of current from a power source at various times during operation. For example, a digital circuit, such as central processing unit (CPU) or digital signal processor (DSP) as examples, may require anywhere from a few milliAmps (mA) to one Amp (1.0 A) during operation depending on the type of operations being performed. The digital circuit may demand higher current levels during high current operations, such as when performing floating point operations as an example. The digital circuit may demand lower power levels during other periods, such as during sleep or idle modes, as examples.
Current may be supplied to a circuit by a power supply regulated by a voltage regulator regulating the voltage level supplied to the circuit. Losses may occur in the power supply and the voltage regulator. The ratio of the energy supplied to the digital circuit compared to the total energy consumed by the power supply is the efficiency of the power supply. The efficiency is between zero and one hundred percent (0-100%). Higher efficiencies are desirable to minimize the total system energy consumption required to operate the digital circuit. To minimize these losses and conserve power, power supplies are commonly designed with multiple capacity or current modes. As an example, a power supply may have a high current mode which uses pulse width modulation (PWM) to provide higher output current levels to a circuit. However, the efficiency of the power supply may be less in high current mode than it would be when employing a low current mode using pulse frequency modulation (PFM) to provide lower output current levels to a circuit. Thus, if the current level requirements of a circuit can be provided by a low current mode of the power supply, less loss will occur if the power supply is operated in low current mode as opposed to high current mode.
In this regard, it may be advantageous to configure a power supply providing power for a circuit into a low current mode to increase efficiency and reduce power losses as a result. For example, the power supply may be switched to low current mode when the circuit is placed in a sleep mode and current demand is within low current mode specifications. When the circuit is placed in a wake mode, as an example, the power supply can be switched to high current mode to supply higher current levels to the circuit. There may be times when current demand by the circuit is within low current mode specifications during wake or normal operating modes. If the power supply is placed in low current mode during these times, and the circuit subsequently demands higher current levels than can be supplied by the power supply in the low current mode, the power supply must be switched to a high current mode. However, detection of the increased current level demand by the circuit and switching of the power supply from low current mode to high current mode may not be completed before the circuit requires higher current levels. Power supply disruptions can occur, and performance issues or malfunctions can occur in the digital circuit as a result. Even with techniques that predict increases in current demand, the actual current demand by the circuit may vary and may not be reasonably predictable.
Thus, the circuit is operated in wake or normal operating modes with the power supply configured in high current mode to avoid performance issues due to power supply disruptions, even when the current demands of the circuit are usually within the low current mode specifications of the power supply. This causes the power supply to have excess capacity that can reduce efficiency of the power supply as a result since the circuit does not always require the high current mode of the voltage regulator.